1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to such a device having two semiconductor chips mounted over both surfaces of a wiring substrate. The present invention may also relate to a method of manufacturing such a device.
2. Background
Recently, a semiconductor device including a plurality of semiconductor chips flip-chip mounted on a rigid substrate has been proposed. For example, Japanese Patent Application Laid-Open No. 2006-210566 discloses a semiconductor device of a type that semiconductor chips are flip-chip mounted respectively on both surfaces of a wiring substrate. When the semiconductor chips are flip-chip mounted respectively on the both surfaces of the substrate in this manner, packaging of a higher density is enabled.
However, in the semiconductor device described in Japanese Patent Application Laid-Open No. 2006-210566, since the semiconductor chip and external terminals are disposed on a single flat surface (back surface) of the substrate, the difference in the heights of the back surface of the semiconductor chip and the distal ends of the external terminals, i.e., a so-called standoff is extremely small. Therefore, there has been a problem that it is difficult to mount that on a substrate surface having asperities. The substrate surface having asperities corresponds to, for example, the surface of a lower-side package of a semiconductor device having a PoP (Package on Package) structure. Therefore, it is difficult to use the semiconductor device described in Japanese Patent Application Laid-Open No. 2006-210566 as an upper-side package of a semiconductor device having the PoP structure.
In order to solve such a problem, there is a conceivable method in which conductive posts are projected from a wiring substrate like a semiconductor device described in Japanese Patent Application Laid-Open No. 2007-287906. However, sometimes there has been a case in which, when the conductive posts are projected from the wiring substrate, the standoff becomes excessive depending on the structure of a lower-side package, and the overall thickness is increased more than needed. Moreover, since the semiconductor device described in Japanese Patent Application Laid-Open No. 2007-287906 is not for mounting or flip-chip mounting semiconductor chips on both surfaces of the substrate, it is unknown how it should be applied to a semiconductor device of a type in which semiconductor chips are flip-chip mounted respectively on both surfaces of a wiring substrate.
Moreover, although it is not a semiconductor device including flip-chip mounted semiconductor chips, Japanese Patent Application Laid-Open No. 2010-103348 discloses a structure in which: semiconductor chips are respectively mounted on both surfaces of a wiring substrate, these semiconductor chips are covered with a sealing resin in order to suppress warpage of the semiconductor device, and the wiring substrate and external terminals are connected via through-hole conductors provided to penetrate through the sealing resin. However, if the semiconductor chips are to be flip-chip mounted on the wiring substrate, a process such as pressing the semiconductor chips against the wiring substrate while applying load and ultrasonic waves is required; however, since the semiconductor device described in Japanese Patent Application Laid-Open No. 2010-103348 employs wire bonding, a problem specific to flip-chip mounting, for example, a problem such as deformation of the wiring substrate due to application of load and ultrasonic waves is not caused.
Furthermore, even if the sizes of first and second memory chips on the upper and lower surfaces of the wiring substrate and the thicknesses of first and second sealing resins on the upper and lower surfaces of the wiring substrate are the same, disposing a plurality of conductive posts around the layer of the second sealing resin on the lower surface of the wiring substrate may cause the layer of the second sealing resin on the lower surface of the wiring substrate to be smaller than the layer of the first sealing resin on the upper surface of the wiring substrate and may cause minus warpage (concave warpage) in a package in an upper level. If the package in a lower level is plus-warped (convex warped) and the minus warpage of the package in the upper level is large, the warpage directions of the packages in the upper and lower levels become mutually opposite, and the package in the upper level cannot be mounted for lamination on the package in the lower level.